1. Field of the Invention
This invention relates to an oxide etching method, and more particularly to a method of etching oxide using low-medium density plasma to form a self-aligned contact (SAC).
2. Description of Related Art
In the current semiconductor fabrication processes, because the integration of an integrated circuit (IC) is very high, an IC chip no longer has adequate surface area for making the large number of required interconnects. In order to make the required interconnects used for connecting large numbers of reduced-dimension metal-oxide semiconductor (MOS) transistors, an IC design including two metal layers of interconnects is gradually becoming widely used. A contact opening for electrically connecting the metal layers has therefore been developed.
However, because the distance between each element in the MOS device is usually quite small, misalignment often occurs during pattern transfer. This causes unexpected etching on the metal layers in a subsequent etching process and results in a short circuit or current leakage. A self-aligned contact (SAC) has therefore been developed to solve the misalignment problem.
Current semiconductor technology has achieved sub-micron dimensions. Under this technology, the formation of SAC is more critical to the fabrication of a logic device, a DRAM device or a SRAM device. The SAC can currently be formed by low-medium density plasma oxide etchings, such as magnetic enhanced reactive ion etching (MERIE), reactive ion etching (RIE), or IEM.
FIG. 1A and FIG. 1B are cross-sectional views schematically illustrating a conventional oxide etch using low-medium density plasma. In FIG. 1A, a gate 102 with a spacer 104 on both sides is formed over a semiconductor substrate 100. The gate 102 in the conventional example is schematically shown as two gates 102. The spacer 104 includes, for example, silicon nitride. Next, an oxide layer 106 is formed over the substrate 100 by, for example, chemical vapor deposition (CVD). Next, a photoresist layer (not shown) is coated over the oxide layer 106 and is patterned to form a first photoresist layer 108a, which covers the gates 102 region, and a second photoresist layer 108b. The first photoresist layer 108a has an opening 109a, located above and between the gates 102. The second photoresist layer 108b has a wider opening 109b.
In FIG. 1A and FIG. 1B, the oxide layer 106 is patterned, according to the first photoresist layer 108a, to form a contact opening 110, which exposes the substrate 100 and the spacer 104 between the gates 102. The oxide layer 106 is patterned, according to the second photoresist layer 108b, to form a monitoring opening 112, which is wider than the contact opening 110. The patterning process includes, for example, using a MERIE oxide etching with an etchant of a mixed gas of C.sub.4 F.sub.8 /CO/Ar. This mixed gas has a higher etching selectivity on the oxide layer 106 than on the spacer 104 so that the spacer 104 remains intact.
The photoresist layer 108a and 108b are usually made of polymer, and polymer can react with the etchant to produce carbolic particles which get dumped into the monitoring opening 112. A micro-loading may then occur in the monitoring opening 112 which degrades the subsequent etching efficiency so that the monitoring opening 112 as shown in FIG. 1B doesn't expose the substrate 100 and the daily quality measurement cannot effectively be monitored. The end result is that the IC chip quality cannot be effectively controlled.